View CY2318ANZ_164943.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY2318ANZ
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs
Features
* One input to 18 output buffer/driver * Supports up to four SDRAM DIMMs * Two additional outputs for feedback * Serial interface for individual output control * 150ps typical output-output skew * Up to 100 MHz operation * Dedicated OE pin for testing * Space-saving 48-pin SSOP package * 3.3V operation
Functional Description
The CY2318ANZ is a 3.3V buffer designed to distribute high-speed clocks in PC applications. The part has 18 outputs, 16 of which can be used to drive up to four SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium II(R) processors. The CY2318ANZ can be used in conjunction with the CY2280, CY2281, CY2282 or similar clock synthesizer for a complete Pentium II motherboard solution. The CY2318ANZ also includes a serial interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull up). A separate Output Enable pin facilitates testing on ATE.
Block Diagram
Pin Configuration
SSOP Top View
BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17 OE
SDATA Serial Interface Decoding SCLOCK
NC NC VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD SDRAM4 SDRAM5 VSS VDD SDRAM6 SDRAM7 VSS VDD SDRAM16 VSS VDDIIC SDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC VDD SDRAM15 SDRAM14 VSS VDD SDRAM13 SDRAM12 VSS OE VDD SDRAM11 SDRAM10 VSS VDD SDRAM9 SDRAM8 VSS VDD SDRAM17 VSS VSSIIC SCLOCK
Cypress Semiconductor Corporation Document #: 38-07181 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 19, 2005
CY2318ANZ
Pin Summary
Name VDD VSS VDDIIC VSSIIC BUF_IN OE SDATA SCLK SDRAM [0-3] SDRAM [4-7] SDRAM [8-11] Pins 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 23 26 11 38 24 25 4, 5, 8, 9 13, 14, 17, 18 31, 32, 35, 36 Description 3.3V Digital voltage supply Serial interface voltage supply Ground for serial interface Input clock (5V Tolerant) Output Enable (active HIGH), Three-state outputs when low[1] Serial data input[1] Serial clock input[1] SDRAM byte 0 clock outputs SDRAM byte 1 clock outputs SDRAM byte 2 clock outputs SDRAM byte 3 clock outputs SDRAM clock outputs usable for feedback Reserved for future modifications, do not connect in system
6, 10, 15, 19, 22, 27, 30, 34, 39, 43 Ground
SDRAM [12-15] 40, 41, 44, 45 SDRAM [16-17] 21, 28 N/C 1, 2, 47, 48
Note: 1. Internal pull-up resistor to VDD (value > 100 kohms)
Device Functionality
OE 0 1 SDRAM [0-17] Hi-Z 1 x BUF_IN
Document #: 38-07181 Rev. *B
Page 2 of 9
CY2318ANZ
Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits should be programmed to "0". * Serial interface address for the CY2318ANZ is:
* *
Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Pin # 45 44 41 40 36 35 32 31 Description SDRAM15 (Active/Inactive) SDRAM14 (Active/Inactive) SDRAM13 (Active/Inactive) SDRAM12 (Active/Inactive) SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive)
A6 1
* *
A5 1
A4 0
A3 1
A2 0
A1 0
A0 1
R/W ----
Bit 0
Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 21 ------Description SDRAM17 (Active/Inactive) SDRAM16 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0
Byte 0:SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Bit 7 18 Bit 6 17 Bit 5 14 Bit 4 13 Bit 3 9 Bit 2 8 Bit 1 5 Bit 0 4
Document #: 38-07181 Rev. *B
Page 3 of 9
CY2318ANZ
Maximum Ratings
Supply Voltage to Ground Potential ..................-0.5 to +7.0V DC Input Voltage (except BUF_IN) .......... -0.5V to VDD + 0.5 DC Input Voltage (BUF_IN).............................. -0.5V to 7.0V Storage Temperature .................................. -65C to +150C Junction Temperature ............................................... +150C Static Discharge Voltage............................................ >2000V (per MIL-STD-883, Method 3015)
Operating Conditions
Parameter VDD, VDDIIC TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min. 3.135 0 20 Max. 3.465 70 30 7 50 Unit V C pF pF ms
Electrical Characteristics Over the Operating Range
Parameter VIL VILiic VIH IIL IIL IIH VOL VOH IDD IDD IDD IDD IDDS Description Input LOW Voltage[2] Test Conditions For all pins except serial interface pins For serial pins only 2.0 VIN = 0V VIN = 0V VIN = VDD IOL = 25 mA IOH = -36 mA Unloaded outputs, 100 MHz Loaded outputs, 100 MHz Unloaded outputs, 66.67 MHz Loaded outputs, 66.67 MHz BUF_IN = VDD or VSS, all other inputs at VDD 2.4 200 360 150 230 500 -10 -10 10 100 10 0.4 Min. Max. 0.8 0.7 Unit V V V A A A V V mA mA mA mA A
Input LOW Voltage Input HIGH Voltage[2] Input LOW Current (BUF_IN input) Input LOW Current (Except BUF_IN Pin) Input HIGH Current Output LOW Supply Supply Voltage[3] Output HIGH Voltage[3] Current[3] Current[3] Supply Current Supply Current Supply Current
Notes: 2. BUF_IN input has a threshold voltage of VDD/2. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document #: 38-07181 Rev. *B
Page 4 of 9
CY2318ANZ
Switching Characteristics[4]
Parameter Duty Cycle t3 t4 t5 t6 t7 t8 t9 Name Maximum Operating Frequency
[3, 5]
Test Conditions Measured at 1.5V Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V
[3] [3]
Min. 45.0 0.9 0.9 1.0 1.0 1.0 1.0
Typ. 50.0 1.5 1.5 150 3.5 3.5 5 20
Max. 100 55.0 4.0 4.0 250 5.0 5.0 12 30
Unit MHz % V/ns V/ns ps ns ns ns ns
= t2 / t1
Rising Edge Rate[3] Falling Edge Rate[3] Output to Output Skew SDRAM Buffer LH Prop. Delay SDRAM Buffer Enable Delay
All outputs equally loaded Input edge greater than 1 V/ns Input edge greater than 1 V/ns Input edge greater than 1 V/ns Input edge greater than 1 V/ns
SDRAM Buffer HL Prop. Delay[3]
[3] [3]
SDRAM Buffer Disable Delay
Switching Waveforms
Duty Cycle Timing
t1 t2 1.5V 1.5V 1.5V
All Outputs Rise/Fall Time
2.4V 0.4V t3 2.4V 0.4V t4 3.3V 0V
OUTPUT
Output-Output Skew
OUTPUT
1.5V
OUTPUT t5
1.5V
Notes: 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Document #: 38-07181 Rev. *B
Page 5 of 9
CY2318ANZ
Switching Waveforms (continued)
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT t6 t7
SDRAM Buffer Enable and Disable Times
OE Three-State OUTPUTS t8
Active t9
Test Circuit VDD 0.1 F
OUTPUTS
CLK out CLOAD
GND
Document #: 38-07181 Rev. *B
Page 6 of 9
CY2318ANZ
Application Circuit
+3.3V
Rs
CPUCLK
BUF_IN
VDD
0.1 F
VDDIIC
0.1 F
CY2280: 48-pin SSOP
Rs
SDRAM[0:17]
SDRAM[0:17]
Ct
SDATA SCLK
VssIIC Vss
CY2318ANZ: 48-pin SSOP
Rs = Series termination resistor Ct = Optional cap to reduce EMI
Ordering Information
Ordering Code CY2318ANZPVC-11 CY2318ANZPVC-11T Lead-free CY2318ANZOXC-11 CY2318ANZOXC-11T 48-pin SSOP 48-pin SSOP- Tape and Reel Commercial Commercial 48-pin SSOP 48-pin SSOP - Tape and Reel Package Type Operating Range Commercial Commercial
Document #: 38-07181 Rev. *B
Page 7 of 9
CY2318ANZ
Package Diagram
48-Lead Shrunk Small Outline Package O48
51-85061-*C
Pentium II is a registered trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07181 Rev. *B
Page 8 of 9
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2318ANZ
Document History Page
Document Title: CY2318ANZ 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs Document Number: 38-07181 REV. ** *A *B ECN NO. 111857 121833 310577 Issue Date 12/09/01 12/14/02 See ECN Orig. of Change DSG RBI RGL Description of Change Change from Spec number: 38-00771 to 38-07181 Power up requirements added to Operating Conditions Information Added Tape and Reel option Added Lead-free Devices
Document #: 38-07181 Rev. *B
Page 9 of 9

▲Up To Search▲

Price & Availability of CY2318ANZ

	To Download CY2318ANZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .